how a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate) and stealthy (i.e., requires an unlikely trigger sequence before effecting a chip’s functionality).
In the past years, I reviewed stage0 of live-bootstrap and gave two presentations about it (available on YouTube). Currently, I am working on a much simpler approach than using the GNU Mes compiler, which requires you to first have a large subset of C compiler. See https://www.iwriteiam.nl/Software.html for more information.
>a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate)
Huh... I'm no EE, but measuring the complexity of an analog circuit in gates seems odd to me. For starters, the added circuitry isn't just one gate. There's a few capacitors added as well. And something tells me if someone were to add a parasitic circuit like that, it'd have to link up all over the parent circuit to probe voltages. Obviously it wouldn't be noticeable in a finished product (much less in an IC), but I wonder how noticeable it would be at the design stage by other humans.
how a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate) and stealthy (i.e., requires an unlikely trigger sequence before effecting a chip’s functionality).
Surprisingly no mention of the Z80 "trap gates" in that section, as it's extremely relevant: https://retrocomputing.stackexchange.com/questions/11143/in-...
In the past years, I reviewed stage0 of live-bootstrap and gave two presentations about it (available on YouTube). Currently, I am working on a much simpler approach than using the GNU Mes compiler, which requires you to first have a large subset of C compiler. See https://www.iwriteiam.nl/Software.html for more information.
>a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate)
Huh... I'm no EE, but measuring the complexity of an analog circuit in gates seems odd to me. For starters, the added circuitry isn't just one gate. There's a few capacitors added as well. And something tells me if someone were to add a parasitic circuit like that, it'd have to link up all over the parent circuit to probe voltages. Obviously it wouldn't be noticeable in a finished product (much less in an IC), but I wonder how noticeable it would be at the design stage by other humans.
Related: https://news.ycombinator.com/item?id=45564203